High performance embedded dram technology with strained silicon

ABSTRACT

Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device ( 66, 68, 70 ), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

FIELD OF THE INVENTION

The field of the invention is semiconductor processing. Specifically,the invention relates to forming semiconductor devices in a strainedlayer region and a strained layer-free region of the same substrate.

BACKGROUND OF THE INVENTION

Semiconductor devices such as Metal-Oxide-Semiconductor Field EffectTransistors (MOSFET's) formed on strained silicon channels have beenshown to offer dramatic improvements in mobility and performance. Thesuccessful integration of high-performance strained silicon logic typeMOSPET's with memory such as dense, low-leakage Dynamic Random AccessMemory (DRAM) arrays on the same semiconductor chip for embedded-DRAMapplications has not been achieved due to the need to maintain highquality, defect-free silicon in the DRAM array areas while providingstrained silicon in the logic support areas. Strained silicon and thesubstrate required to produce the strain inherently results in greatlyincreased silicon dislocations, which makes it incompatible withlow-leakage DRAM cells. Furthermore, semiconductor processes whichexceed certain temperatures that are required for the DRAM cellformation may be incompatible with currently practiced strained siliconformation.

Forming high-performance strained silicon support MOSFETs on the samesubstrate with low-leakage high-density DRAM cells is desired.

SUMMARY OF THE INVENTION

It is thus an object of the present invention to form high-performancestrained silicon support MOSFETs on the same substrate with low-leakagehigh-density DRAM cells.

The present invention discloses a first semiconductor device such as,for example, a low-leakage DRAM cell, formed in a strained layer-freeregion of a semiconductor substrate. On the same semiconductorsubstrate, a strained layer region is selectively formed in thesemiconductor substrate separate from the strained layer-free region anda second semiconductor device such as, for example, a high-performanceMOSFET, is formed in the strained layer region.

DESCRIPTION OF THE DRAWING

The foregoing and other features of the invention will become moreapparent upon review of the detailed description of the invention asrendered below. In the description to follow, reference will be made tothe several figures of the accompanying Drawing, in which:

FIGS. 1-8 are cross sectional views of the semiconductor structure as itappears during the steps according to the method of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

Referring to FIG. 1, p-type silicon substrate 10 is provided havingmemory cell 12 formed in a strained layer-free region of substrate 10.In FIG. 1, memory cell 12 is a DRAM cell having a trench storagecapacitor 14 and vertical MOSFET 16, which can be formed, for example,as described in commonly assigned U.S. Pat. No. 6,225,158 B1, hereinincorporated by reference. Although memory cell 12 is shown in FIG. 1 ashaving a trench storage capacitor 14 and vertical MOSFET 16, it shouldbe noted that memory cell 12 can be formed using other types ofcapacitors and FET's such as a stacked capacitor or a planar MOSFET. Inthis example, trench storage capacitor 14 includes: deep trench 18, n+buried plate 20, nitride/oxide node dielectric 22, n+ polysilicon 24 and26, collar oxide 28 and n+ buried strap diffusion 30. Further, verticalMOSFET 16 includes: trench top oxide 32, gate oxide 34 formed on thesidewalls of deep trench 18, and n+ polysilicon gate conductor 36. Itshould be noted that two memory cells 12 are shown in the array regionthroughout FIGS. 1-8. However, it should be understood that any numberof one or more memory cells 12 can be formed in the array region.

After formation of memory cells 12 in strained layer-free regions ofsubstrate 10, strained layer regions are formed in substrate 10 for thesubsequent formation of high performance MOSFETS. Thus, processincompatibilities such as high temperatures used in the formation of thememory cells are avoided since the strained layer regions and theMOSFETS are formed after the memory cells are formed.

A thin layer 40 (e.g. silicon oxide) is deposited on pad film 38 (whichcan include, for example, a pad nitride and a pad oxide layer) andexposed portions of gate conductor 36 as shown in FIG. 2. Oxide layer 40serves as an etch stop layer in subsequent processing.

Another layer 42 (e.g. silicon nitride) is then deposited on oxide layer40, and a hard mask layer 44 (e.g. silicon oxide) is deposited onsilicon nitride layer 42.

A block resist (not shown) is patterned on oxide hard mask layer 44 anda reactive ion etch is used to etch through exposed portions of layers38, 40, 42,44 and into substrate 10 to a preferred depth of about 100 nmto about 400 nm, more preferably about 200 nm, to form trench 46 asshown in FIG. 2. Any remaining block resist is removed from oxide hardmask layer 44 after the formation of trench 46.

Referring to FIG. 3, oxide hard mask layer 44 is removed by a standardprocess, such as reactive ion etching selective to silicon nitride layer42 and silicon exposed by trench 46. Spacer 48 comprising a materialupon which silicon or Silicon Germanium (SiGe) will not nucleate, suchas silicon oxide or nitride, is formed on sidewall surface 50 of trench46, such as by conventional deposition and RIE. A linear graded bufferlayer technique can be used to grow SiGe layer 52 with low dislocationdensity (˜105 cm−2) in trench 46. Growth conditions are favored toselectively form SiGe layer 52 on substrate 10, and not on spacer 48.Preferably, SiGe layer 52 is epitaxially grown upward from exposedbottom surface 54 of trench 46 until SiGe layer 52 is above the topsurface of silicon nitride layer 42. Overgrown SiGe layer 52 isplanarized to the top surface of silicon nitride layer 42 by a processsuch as chemical mechanical polishing (CMP). Silicon CMP processes thatare known in the art can be used to planarize SiGe layer 52.

Optionally, spacer 48 can be omitted, however, spacer 48 prevents SiGelayer 52 from nucleating and epitaxially growing outward from sidewallsurface 50 resulting in two growth fronts in SiGe layer 52. In addition,spacer 48 isolates strain produced by SiGe layer 52 in substrate 10 tothe supports area of the chip, thus isolating the storage capacitorcells in the array from the strain.

Next, upper surface 56 of SiGe layer 52 is selectively recessed by anetch process such as a reactive ion etch using an SF6 gas or anoxidation followed by an HF wet etch to a depth below the upper surfaceof silicon nitride layer 42, as shown in FIG. 4. Optionally, the recessof SiGe layer 52 may be omitted, since the subsequently grown strainedlayer is very thin.

Referring to FIG. 5, a thin layer of epitaxial silicon 58 is selectivelygrown on upper surface 56 of SiGe layer 52. Epitaxial silicon layer 58is grown to a thickness preferably less than about 50 nm, morepreferably from about 2.5 nm to about 10 nm. Due to the lattice mismatchbetween SiGe layer 52 and thin epitaxial silicon layer 58, epitaxialsilicon layer 58 undergoes a tensile lattice strain which enhances themobility of subsequently formed PETs. After the growth of epitaxialsilicon layer 58, silicon nitride layer 42 is removed selective to oxidelayer 40 and epitaxial silicon layer 58 by processes known in the art,such as a wet etch comprising hot phosphoric acid. It should be notedthat strained layer 58 can also be formed by other methods such as, forexample, depositing titanium (Ti) or Cobalt (Co) metal on upper surface56 of SiGe layer 52 and forming a thin layer of titanium silicide orcobalt silicide. Another example of forming strained layer 58 includesimplanting into upper surface 56 of SiGe layer 52 an element having alattice constant different than SiGe such as, for example, carbon (C) orgermanium (Ge).

Referring to FIG. 6, a silicon nitride layer 60 is deposited on oxidelayer 40 and strained silicon layer 58, and it is then patterned toexpose the supports while the arrays remain covered. The active areas inthe supports are patterned to form shallow trench isolations (STI) 62,that are filled using known methods, such as TEOS CVD oxide or HDPoxide, followed by planarizing. Sacrificial oxide (not shown) is grownin the supports and well implants (not shown) are formed. Sacrificialoxide is removed and support gate dielectric 64 is formed on strainedsilicon layer 58 by growing a thin dielectric film, such as thermaloxide or nitrided oxide. Support gate conductor 66 is formed in thestrained layer region (supports), and portions of gate conductor 66remaining in the strained layer region (array) are removed using a blockmask.

Referring to FIG. 7, silicon nitride layer 60 is removed from the arrayselective to oxide layer 40 by methods known in the art, such as a wetetch comprising hot phosphoric acid. Oxide layer 40 is then removedselective to silicon nitride layer 38. Wordline conductor 68, such astungsten/tungsten silicide, and cap layer such as silicon nitride 70,are deposited in the support and array regions.

Referring to FIG. 8, support gate 66, wordlines 68 and cap layer 70 aresimultaneously patterned and etched with a common mask. Optionally, twomasks could be used to form support gate 66 and wordlines 68. Forexample, one mask could be used to form support gate 66 while anothermask could be used to form wordlines 68 in order to individuallyoptimize specific properties of each, such as linewidth for performanceconsiderations.

Standard processing follows, which includes: support S/D extension, haloand contact implants; gate sidewall oxidation to heal any damage due togate etch; spacer formation; support and bitline contact studs;interlevel dielectrics; and, deposition and patterning of upper layersof wiring, including bitline conductors.

Additionally, if propagation of silicon dislocations from the strainedlayer SiGe region into the strained layer-free memory array is aconcern, dummy deep storage trenches may be used as a buffer between thestrained layer (supports) and the strained layer-free (array) regions.

While the invention has been described above with reference to thepreferred embodiments thereof, it is to be understood that the spiritand scope of the invention is not limited thereby. Rather, variousmodifications may be made to the invention as described above withoutdeparting from the overall scope of the invention as described above andas set forth in the several claims appended hereto.

1. A semiconductor structure comprising: a semiconductor substratehaving a strained layer-free region and a strained layer region; a firstdevice formed in the strained layer-free region of the semiconductorsubstrate; and a second device formed in the strained layer region ofthe semiconductor substrate.
 2. The semiconductor structure of claim 1,wherein the first device comprises a memory cell and the second devicecomprises an FET.
 3. The semiconductor structure of claim 2, wherein thememory cell is a low-leakage DRAM cell and the FET is a MOSFET logicdevice.
 4. The semiconductor structure of claim 1, wherein the strainedlayer region has a trench selectively formed in the substrate, andcomprises: a SiGe layer formed in the trench, and an epitaxial siliconlayer formed on the SiGe layer.
 5. The semiconductor structure of claim4, wherein the epitaxial silicon layer is from about 2.5 to about 10 nmthick.
 6. The semiconductor structure of claim 4, wherein the SiGe layeris epitaxially grown.
 7. The semiconductor structure of claim 4, whereinthe strained layer region further comprises a spacer formed on asidewall of the trench, the spacer isolating strain produced in thestrained layer region from the strained layer-free region.
 8. Thesemiconductor structure of claim 4, wherein the trench is from about 100nm to about 400 nm deep.
 9. A method for fabricating a semiconductorstructure comprising the steps of: a) providing a semiconductorsubstrate having a strained-layer free region; b) forming a first devicein the strained layer-free region of the semiconductor substrate; c)selectively forming a strained layer region in the semiconductorsubstrate; and d) forming a second device in the strained layer region.10. The method of claim 9, wherein step (c) further comprises: i)forming a trench having a bottom surface and a sidewall surface; ii)forming a layer of SiGe in the trench; and iii) forming a layer ofsilicon on the layer of SiGe.
 11. The method of claim 10, wherein step(ii) comprises epitaxially growing the layer of SiGe.
 12. The method ofclaim 10, wherein step (iii) comprises epitaxially growing the layer ofsilicon.
 13. The method of claim 10, wherein the layer of silicon isfrom about 2.5 nm to about 10 nm thick.
 14. The method of claim 10,wherein after step (i), forming a spacer on the sidewall surface. 15.The method of claim 9, wherein the first device comprises a memory celland the second device comprises an FET.
 16. The method of claim 15,wherein the memory cell is a low-leakage DRAM cell and the FET is aMOSFET logic device.